DocumentCode
450682
Title
Rule-Based VLSI Verification System Constrained by Layout Parasitics
Author
Wenin, Jacques ; Verhasselt, Johan ; Van Camp, Marc ; Guebels, Pierre ; Leonard, Jean
Author_Institution
Bell Alcatel - Antwerp, VLSI Department, Francis Wellesplein, Antwerp, Belgium
fYear
1989
fDate
25-29 June 1989
Firstpage
662
Lastpage
667
Abstract
This paper addresses a rule-based method for VLSI design review, constrained by parasitics. Using the new ideas discussed in this paper, extraction from layout is not limited anymore to conventional electrical data, but additionally allows modelling of functional and timing behaviour. An extendable rule based validation algorithm operates on extracted models, decorated with parasitic effects, to formally prove most aspects of design correctness.
Keywords
Circuit simulation; Data mining; Design automation; Design methodology; Expert systems; Packaging; Permission; Timing; Topology; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1989. 26th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-310-8
Type
conf
DOI
10.1109/DAC.1989.203481
Filename
1586465
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