DocumentCode
450683
Title
Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator
Author
Benkoski, Jacques ; Strojwas, Andrzej J.
Author_Institution
SRC-CMU Research Center for CAD, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
fYear
1989
fDate
25-29 June 1989
Firstpage
668
Lastpage
673
Abstract
A new multi-level macromodeling technique for timing simulation has been developed. This technique is based upon the modeling of the behavior of subcircuits under single input changes. The possible interactions between multiple input changes determine the range of validity of the models. A formal method for developing the model validity conditions is presented. This work establishes a bridge between timing analysis by using single input change models, and timing simulation which correctly models signal interactions. The availability of a formal criterion for the validity of the models allows the dynamic identification of the parts of the circuit that require more accurate models. As a result, the cost advantage of high level models can be fully exploited while still allowing critical interactions to be simulated with high accuracy.
Keywords
Analytical models; Bridge circuits; Circuit simulation; Computational modeling; Computer simulation; Costs; Permission; Propagation delay; Signal analysis; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1989. 26th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-310-8
Type
conf
DOI
10.1109/DAC.1989.203482
Filename
1586466
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