• DocumentCode
    450722
  • Title

    Loop Optimization in Register-Transfer Scheduling for DSP-Systems

  • Author

    Goossens, Gert ; Vandewalle, Joos ; Man, Hugo De

  • Author_Institution
    IMEC Laboratory, Leuven, Belgium
  • fYear
    1989
  • fDate
    25-29 June 1989
  • Firstpage
    826
  • Lastpage
    831
  • Abstract
    In this paper, we discuss a control-flow transformation called loop folding, during the scheduling of register-transfer code for DSP-systems. Loop folding is functionally equivalent to data-path pipelining. An iterative loop-folding procedure, implemented in the CATHEDRAL II compiler, is presented. This technique may significantly improve the utilization of parallel hardware, available in a data path.
  • Keywords
    Compaction; Concurrent computing; Digital signal processing; Hardware; Laboratories; Parallel processing; Permission; Pipeline processing; Signal synthesis; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1989. 26th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-310-8
  • Type

    conf

  • DOI
    10.1109/DAC.1989.203521
  • Filename
    1586505
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=450722