• DocumentCode
    451405
  • Title

    Timing-driven Steiner tree construction with buffer insertion

  • Author

    Yan, Jin-Tai ; Wang, Tzu-Ya ; Lee, Chia-Fang

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Chung Hua Univ., Hsinchu
  • fYear
    2005
  • fDate
    7-10 Aug. 2005
  • Firstpage
    247
  • Abstract
    In this paper, given a set of connecting nodes in a signal net, based on the concept of sharing-buffer insertion and hidden Steiner-point assignment, an effective timing-driven rectilinear Steiner tree with buffer insertion (TRST/BI) approach is proposed to construct a timing-driven rectilinear Steiner tree by introducing sharing-buffers and hidden Steiner points onto feasible positions. The experimental results show that our proposed TRST/BI approach obtains better timing-driven Steiner trees than our previous TRST approach for the tested signal nets
  • Keywords
    buffer circuits; network routing; timing; trees (mathematics); hidden Steiner points; sharing-buffer insertion; timing-driven rectilinear Steiner tree; Bismuth; Capacitance; Computer science; Delay; Joining processes; Routing; Signal design; Testing; Timing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2005. 48th Midwest Symposium on
  • Conference_Location
    Covington, KY
  • Print_ISBN
    0-7803-9197-7
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2005.1594085
  • Filename
    1594085