A 8-channels low-noise CMOS circuit for silicon detectors with on-chip front-end JFET

We propose a CMOS circuit designed to be used with silicon drift detectors (SDDs) coupled to scintillators for γ-ray imaging applications. The circuit is composed by 8 analog channels, each including a low-noise preamplifier, a 6th order semiGaussian shaping amplifier with four selectable peaking times from 1.8 μs up to 6 μs, a peak stretcher and a baseline holder. The integrated time constant used for the shaping are implemented by means of a recently proposed ´RC´ cell. This cell is based on the de-magnification of the current flowing in a resistor R by means of the use of current mirrors. The 8 analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of the channels, trigger output and the programming of independent threshold on the analog channels by means of a programmable serial register and 3-bit DACs. In this work, the main features of the circuit are first presented. The experimental results obtained in the characterization of the prototype are then reported and discussed. The energy resolution measured using a single channel of the chip with a silicon drift detector droplet (SDD³) is of 128 eV at 6 keV with the detector cooled at -20°C.