A fundamental data acquisition saving block

A general data acquisition architecture, allowing a clean conceptual separation of the fundamental blocks in a data acquisition setup, is presented. The approach taken surfaced from a study of several modern architectures and from experience acquired while developing an object-oriented programming solution for a previously developed high-speed architecture. This process of software development leaded naturally to a concept where a net separation between data transfer, and control and trigger signals, suggested a similar general decomposition of the data acquisition hardware, in such a way that the same fundamental hardware blocks can be used in several different configurations. In this paper we report on the strategy and results obtained while developing in VHDL such an important and fundamental unit of the data acquisition chain as the data acquisition saving block. The solution proposed for the data saving block, tested using field programmable gate arrays, implements pre- and post-trigger functionality, supports continuous data streams up to hundreds of MHz, has a large memory pool (hundreds of megabytes), and has an interface capable of providing, upon request, a block of data from a specified address without interfering with the data saving process