• DocumentCode
    451855
  • Title

    Elimination of Dynamic Hazards by Factoring

  • Author

    Moon, Cho W. ; Brayton, Robert K.

  • Author_Institution
    Lattice Semiconductor, Santa Clara, CA
  • fYear
    1993
  • fDate
    14-18 June 1993
  • Firstpage
    7
  • Lastpage
    13
  • Abstract
    We propose a novel method to eliminate dynamic hazards in asynchronous circuits synthesized from the signal transition graph (STG) specifications. We first review a relationship between syntactic constraints such as liveness and complete state coding at the STG level and the hazard properties at the gate level. Using this relationship, we identify the cause of dynamic hazards and remove them by an iterative factoring method. Each factoring entails augmenting the given STG with an internal signal. This method is applicable to both combinational and sequential circuits, and results in hazard-free multi-level implementations from STG specifications.
  • Keywords
    Circuit testing; Combinational circuits; Concurrent computing; Delay; Hazards; Iterative methods; Latches; Sequential circuits; Signal synthesis; Strontium;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1993. 30th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-577-1
  • Type

    conf

  • DOI
    10.1109/DAC.1993.203911
  • Filename
    1600184