DocumentCode :
451857
Title :
Minimal Shift Counters and Frequency Division
Author :
Tokarnia, Alice M.
Author_Institution :
Department of Electrical Engineering, Stanford University, Stanford, CA
fYear :
1993
fDate :
14-18 June 1993
Firstpage :
19
Lastpage :
24
Abstract :
The objective of this paper is to adapt minimal shift counters to frequency division and other applications that require only an indication that a counter has gone through a complete cycle. These applications place no requirement on the coding of the states in the cycle. The indication that a counter has completed a cycle is implemented with a minimum-fan-in AND gate to preserve the high speed and small area that distinguish minimal shift counters.
Keywords :
Counting circuits; Design automation; Design methodology; Distributed computing; Frequency conversion; Machinery; Programmable logic arrays; Sequential circuits; Shift registers; State feedback;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1993. 30th Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-577-1
Type :
conf
DOI :
10.1109/DAC.1993.203913
Filename :
1600186
Link To Document :
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