Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs

We address the problem of technology mapping for generalized fundamental-mode asynchronous designs. In this design style we can separate the combinational portions of the design from the sequential portions, similar to synchronous design styles. We examine each step of algorithmic technology mapping for its influence on the hazard behavior of the modified network. We then present modifications to an existing synchronous technology mapper to work for this asynchronous design style. We present efficient algorithms for hazard analysis that are used during the mapping process. These algorithms have been implemented and incorporated into the program CERES to produce a technology mapper suitable for asynchronous designs.