VIPER: An Efficient Vigorously Sensitizable Path Extractor

Fast and correct timing verification is a critical issue in VLSI design. Several timing verification algorithms have been proposed in the last few years. However, due to the huge computation time needed to eliminate false paths, existing algorithms have difficulty in performing timing verification for large circuits. This paper presents an efficient timing verification algorithm, with a new sensitization criterion, which directly identifies the critical path without eliminating false paths from a path list. The inputs which sensitize the critical path are determined as well.