Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions

We propose a general circuit delay model that unifies all previous delay models, e.g. floating, viability, and transition delays, and models introduced in this paper, e.g. delays by sequences of vectors and minimum delays. Then, we formulate the computation of the exact circuit delays, under both bounded and unbounded gate delay models, as a mixed Boolean linear programming using a new formulation technique, called Timed Boolean Function. Next, we compute the exact delays of combinational circuits for transition delay and delay by sequences of vectors. We show that delays by sequences of vectors and floating (or viability) delays are invariant under both bounded and unbounded gate delay models. Finally, we address the effect of gate delay lower bounds on delays of circuits. We demonstrate the effectiveness of the method by giving exact delay results for all ISCAS benchmark circuits (except C6188).