Title :
Analog System Verification in the Presence of Parasitics Using Behavioral Simulation
Author :
Liu, Edward W Y ; Chang, Henry C. ; Sangiovanni-Vincentelli, Alberto L.
Author_Institution :
Department of EECS, University of California, Berkeley, CA
Abstract :
In analog system design, final verification in the presence of parasitic loading effects is crucial to guarantee functionality of the entire circuit. In this paper, we present a methodology for analog system verification in the presence of parasitics using behavioral simulation. When applied to a synthesized 10 bit D/A, our approach is accurate to 0.005 LSB compared with SPICE, while being several orders of magnitude faster.
Keywords :
Analytical models; Circuit simulation; Circuit synthesis; Computational modeling; Degradation; Design methodology; Integrated circuit interconnections; Routing; SPICE; System performance;
Conference_Titel :
Design Automation, 1993. 30th Conference on
Print_ISBN :
0-89791-577-1
DOI :
10.1109/DAC.1993.203938
