• DocumentCode
    451887
  • Title

    An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation.

  • Author

    Woo, Nam-Sung ; Kim, Jaeseok

  • Author_Institution
    AT&T Bell Laboratories, Murray Hill, NJ
  • fYear
    1993
  • fDate
    14-18 June 1993
  • Firstpage
    202
  • Lastpage
    207
  • Abstract
    We developed a new method, called MP2, for partitioning networks into multiple (> 2) blocks each of which has both size and pin constraints. The MP2 method uses an improvement approach and tries to minimize the total number of terminals of all blocks while satisfying the pin and size constraints of every block. It supports multiple classes of cells in input networks and blocks. It makes use of a scalar value of benefit which captures lookahead information. It is the first improvement method that considers pin constraints of blocks. It has been applied to partitioning technology-mapped circuits into multiple FPGA chips. In addition to describing the MP2 method, we will discuss some interesting findings we gleaned during our experiments.
  • Keywords
    Bismuth; Decoding; Field programmable gate arrays; Hardware; Logic circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1993. 30th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-577-1
  • Type

    conf

  • DOI
    10.1109/DAC.1993.203946
  • Filename
    1600219