Non-Scan Design-for-Testability Techniques for Sequential Circuits

Recent studies show that a stuck-at test applied at the operational speed of the circuit identifies more defective chips than a test having the same fault coverage but applied at a lower speed. In this work, we investigate various design-for-testability (DFT) techniques for sequential circuits which permit at-speed application of tests while providing for very high fault coverage. The method involves parallel loading of flip-flops in test mode for enhanced controllability combined with probe point insertion for enhanced observability. Selection of candidate flip-flops and probe points is determined automatically by our OPUS-NS tool. Fault coverage and ATG effectiveness improved to greater than 96% and 99.7%, respectively, for the ISCAS89 sequential benchmark circuits studied when these non-scan DFT techniques were used.