Evaluation by Parts of Mixed-Level DC-Connected Components in Logic Simulation

This paper describes an evaluation-by-parts technique for logic simulation of mixed-level MOS digital circuits. An accurate model is proposed to replace subcircuits in the mixed-level description of partitioned dc-connected components. The replacement converts a mixed-level dc-connected component into a switch-level circuit. A new switch-level nodal analysis technique is presented which evaluates the logic state and strength of nodes in switch-level circuits. The main feature of this technique is the improvement of simulation accuracy and efficiency. Experimental results show significant speed-up for the evaluation of large mixed-level dc-connected components.