• DocumentCode
    451927
  • Title

    Design for Testability for Path Delay Faults in Sequential Circuits

  • Author

    Chakraborty, Tapan J. ; Agrawal, Vishwani D. ; Bushnell, Michael L.

  • Author_Institution
    AT&T Bell Laboratories, Princeton, NJ
  • fYear
    1993
  • fDate
    14-18 June 1993
  • Firstpage
    453
  • Lastpage
    457
  • Abstract
    We experimentally study the reasons for low coverage of path delay faults in several sequential benchmark circuits. Causes for undetected faults are classified into three categories: (A) Combinationally nonactivated paths, (B) Sequentially nonactivated paths, and (C) Unobservable fault effect. The type A faults can only be made detectable by modifying or resynthesizing the combinational logic as has been discussed by others. We find that almost 80% of sequentially untested faults are in category B. Most are not activated because the two successive states necessary to create a transition and to propagate it through the path cannot be produced in the sequential circuit. We study the partial scan technique in which flipflops are scanned to break cycles and show that a substantial increase in the coverage of path delay faults is possible.
  • Keywords
    Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Design for testability; Latches; Logic; Propagation delay; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1993. 30th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-577-1
  • Type

    conf

  • DOI
    10.1109/DAC.1993.203991
  • Filename
    1600264