DocumentCode :
451929
Title :
Minimum Length Synchronizing Sequences of Finite State Machine
Author :
Rho, June-Kyung ; Somenzi, Fabio ; Pixley, Carl
Author_Institution :
Department of Electrical and Computer Engineering, University of Colorado, Boulder
fYear :
1993
fDate :
14-18 June 1993
Firstpage :
463
Lastpage :
468
Abstract :
Computing synchronizing sequences is an important step in test generation for circuits without external reset [CJSP93]. An efficient heuristic algorithm has been recently proposed [PJH92]. However, the only algorithms known so far for the minimum-length synchronizing sequence have been applicable only to small finite state machines, because they required excessive enumeration. In this paper we present a new technique to calculate the minimum length synchronizing sequence of a finite state machine, based on the BDD model of an iterative system. It implicitly calculates all possible minimum length sequences and corresponding reset states by deciding the satisfiability of a boolean formula. We also present a procedure to obtain the synchronizing sequences of a class of sequential iterative systems in constant time regardless of the number of cells. We present experimental results that show the viability of the proposed method for much larger circuits than were tractable by previous exact methods.
Keywords :
Automata; Binary decision diagrams; Boolean functions; Circuit testing; Communication systems; Contracts; Explosions; Heuristic algorithms; Test pattern generators; Transmitters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1993. 30th Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-577-1
Type :
conf
DOI :
10.1109/DAC.1993.203993
Filename :
1600266
Link To Document :
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