Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy

This paper presents FEHSIM, a new hierarchical multi-level fault simulator with switch-level fault models and switch-level accuracy. The simulator is called hierarchical, because it processes hierarchically specified Verilog input files. The simulator is multi-level, because elements may be simulated at the switch-, gate- and register-transfer-level (RT-level). Switch-level accuracy is maintained for the complete circuit, storing the circuit elements multiple times at different levels of abstraction. During simulation, an intelligent scheduling mechanism switches between these levels to force simulation at the highest, thus fastest, possible level of abstraction without loosing switch-level accuracy. The proposed algorithms were implemented in C++ and tested on a large set of benchmark circuits. By using the multi-level mode, the simulator is ten to twenty times faster than in switch-only mode.