• DocumentCode
    451940
  • Title

    Prime: A Timing-Driven Placement Tool Using A Piecewise Linear Resistive Network Approach

  • Author

    Hamada, Takeo ; Cheng, Chung-Kuan ; Chau, Paul M.

  • Author_Institution
    University of California at San Diego, La Jolla, CA
  • fYear
    1993
  • fDate
    14-18 June 1993
  • Firstpage
    531
  • Lastpage
    536
  • Abstract
    An approach toward path-oriented timing-driven placement is proposed. We first transform the placement with timing constraints to a Lagrange problem. A primal-dual approach is used to find the optimal relative module locations. In each primal dual iteration, the primal problem is solved by a piecewise linear resistive network method, while the dual process is used to update the Lagrange multiplier. The sparsity of the piecewise linear resistive network is exploited to obtain dramatic improvement on the efficiency of the calculation. Up to 22.0% of clock cycle reduction was observed for Primary2 test case.
  • Keywords
    Circuits; Clocks; Computational efficiency; Constraint optimization; Delay estimation; Lagrangian functions; Latches; Piecewise linear techniques; Testing; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1993. 30th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-577-1
  • Type

    conf

  • DOI
    10.1109/DAC.1993.204005
  • Filename
    1600278