DocumentCode
451948
Title
Synthesis of Pipelined Instruction Set Processors
Author
Cloutier, Richard J. ; Thomas, Donald E.
Author_Institution
Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
fYear
1993
fDate
14-18 June 1993
Firstpage
583
Lastpage
588
Abstract
This paper presents the Snapshot Method, a technique that fills a void in existing synthesis systems by considering inter-instruction data dependencies while defining a pipeline structure. These dependencies can make it impossible to overlap the execution of some sequences of instructions thus the detection and resolution of such sequences is an important contribution of this work. Experimental results for a design of the IBM ROMP architecture are presented.
Keywords
Assembly; Data engineering; Delay; Design methodology; Design optimization; Hardware; High level synthesis; Pipeline processing; Processor scheduling; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1993. 30th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-577-1
Type
conf
DOI
10.1109/DAC.1993.204014
Filename
1600287
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