• DocumentCode
    451993
  • Title

    Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications

  • Author

    Ashar, Pranav ; Malik, Sharad

  • Author_Institution
    C&C Research Labs, NEC USA, Princeton, NJ
  • fYear
    1994
  • fDate
    6-10 June 1994
  • Firstpage
    77
  • Lastpage
    80
  • Abstract
    The contribution of this paper is an implicit method for computing the minimum cost feedback vertex set for a graph. For an arbitrary graph,we efficiently derive a Boolean function whose satisfying assignments directly correspond to feedback vertex sets of the graph. Importantly, cycles in the graph are never explicitly enumerated, but rather, are captured implicitly in this Boolean function. This function is then used to determine theminimum cost feedbackvertex set. Even though computing theminimumcost satisfying assignment for a Boolean function remains an NP-hard problem, we can exploit the advances made in the area of Boolean function representation in logic synthesis to tackle this problem efficiently in practice for even reasonably large sized graphs. The algorithm has obvious application in flip-flop selection for partial scan. Our algorithm was the first to obtain the MFVS solutions for many benchmark circuits.
  • Keywords
    Benchmark testing; Boolean functions; Circuit synthesis; Circuit testing; Cost function; Feedback; Flip-flops; National electric code; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1994. 31st Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-653-0
  • Type

    conf

  • DOI
    10.1109/DAC.1994.204076
  • Filename
    1600349