DocumentCode
452034
Title
A Methodology and Algorithms for Post-Placement Delay Optimization
Author
Kannan, Lalgudi N. ; Suaris, Peter R. ; Fang, Hong G.
Author_Institution
Escalade Corp., Sunnyvale, CA
fYear
1994
fDate
6-10 June 1994
Firstpage
327
Lastpage
332
Abstract
In this paper we present a placement-intelligent resynthesis methodology and optimization algorithms to meet post-layout timing constraints while at the same time reducing the interconnect congestion. We begin with the synthesized design netlist after initial placement and make incremental modifications - taking placement into account - to generate a final netlist and placement that meets the delay constraints after place and route. The algorithms described have been implemented as part of a tool for placement based resynthesis. The tool has been used with a number of pre-optimized designs from industry and to obtain improvements in post-placement delays ranging from 13 to 22% with improved routability.
Keywords
Application specific integrated circuits; Boolean functions; Delay; Logic; Optimization methods; Permission; Pulse inverters; Routing; Timing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1994. 31st Conference on
ISSN
0738-100X
Print_ISBN
0-89791-653-0
Type
conf
DOI
10.1109/DAC.1994.204121
Filename
1600394
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