• DocumentCode
    452044
  • Title

    RC Interconnect Optimization under the Elmore Delay Model

  • Author

    Sapatnekar, Sachin S.

  • Author_Institution
    Department of Electrical Engineering and Computer Engineering, Iowa State University, Ames, IA
  • fYear
    1994
  • fDate
    6-10 June 1994
  • Firstpage
    387
  • Lastpage
    391
  • Abstract
    An efficient solution to the wire sizing problem (WSP) using the Elmore delay model is proposed. Two formulations of the problem are put forth: in the first, the minimum interconnect delay is sought, while in the second, we minimize the net delay under delay constraints at the leaf nodes; previous approaches solve only the former problem. Theoretical results on these problems are proved, and a sensitivity-based algorithm is devised. It is shown experimentally that the second formulation provides significantly better engineering solutions.
  • Keywords
    Capacitance; Delay; Integrated circuit interconnections; Timing; Upper bound; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1994. 31st Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-653-0
  • Type

    conf

  • DOI
    10.1109/DAC.1994.204131
  • Filename
    1600404