• DocumentCode
    452061
  • Title

    Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications

  • Author

    Bhattacharya, Subhrajit ; Dey, Sujit ; Brglez, Franc

  • Author_Institution
    Dept. of Computer Science, Duke University, Durham, NC
  • fYear
    1994
  • fDate
    6-10 June 1994
  • Firstpage
    491
  • Lastpage
    496
  • Abstract
    This paper presents a new method, based on Markov chain analysis, to evaluate the performance of schedules of behavioral specifications. The proposed performance measure is the expected number of clock cycles required by the schedule for a complete execution of the behavioral specification for any distribution of inputs. The measure considers both the repetition of operations (due to loops) and their conditional execution (due to conditional branches). We propose an efficient technique to calculate the metric. We introduce a loop-directed scheduling algorithm (LDS). The algorithm produces schedules such that the expected number of clock cycles, required by the schedule for a complete execution of the behavioral specification, is minimized. Experimental results on several conditional and loop-intensive specifications demonstrate the relevance and effectiveness of both the performancemeasure and the scheduling algorithm.
  • Keywords
    Clocks; Computer science; National electric code; Optimization methods; Performance analysis; Processor scheduling; Scheduling algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1994. 31st Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-653-0
  • Type

    conf

  • DOI
    10.1109/DAC.1994.204152
  • Filename
    1600425