VFSIM: Vectorized Fault Simulator Using a Reduction Technique Excluding Temporarily Unobservable Faults

A new fault simulator (VFSIM) for synchronous sequential circuits has been developed and applied to random access scan circuits of several hundred LSIs in mainframe computers. The results show that VFSIM is one or two orders of magnitude faster than a conventional fault simulator designed for random access scan circuits. A vectorized pattern parallel event-driven method is introduced for accelerating the fault simulator for synchronous sequential circuits. Utilizing the concept of unobservable regions (UOR), in which simulation of temporarily unobservable faults is avoided, contributes greatly to further acceleration, especially for random access scan circuits.