DocumentCode
452083
Title
A Time Abstraction Method for Efficient Verification of Communicating Systems
Author
Verlind, Eric ; Kolks, Tilman ; De Jong, Gjalt ; Lin, Bill ; Man, Hugo De
Author_Institution
IMEC, Leuven, Belgium
fYear
1994
fDate
6-10 June 1994
Firstpage
609
Lastpage
614
Abstract
An important practical approach to automatic verification of finite state concurrent systems is temporal logic model checking. However, a major barrier towards wider application of suchmethods is the state explosion problem that often occurs during the composition of complex communicating systems. In addition to being large, many systems have very deep state spaces as well. In this paper, we propose an abstraction method based on time abstraction which can significantly reduce both the size as well as the depth of the state space that must be explored during model checking. It is especially suited for applications involving systems that are loosely coupled in the sense that communication activity is relatively sparse, such as applications involving DSPs, which have large intervals of autonomous processing, with communication activity in between. All properties expressiblewith the temporal logic CTL* or CTL* -X are strongly preserved under the proposed abstraction. In particular, we give a method that can replace a chain of states by a single state with atime label . The abstractedmodel is represented by means of atimed label transition system model. We give acomposition algorithm for composing the individually time abstracted models to form a global model that can be converted back to a conventional, but potentiallymuch reduced,state space suitable formodel checking. Furthermore, a similar approach can be followed in dealing with wait states in which a system is idling while waiting for an escape signal. For many cases, our approach is successful in alleviating the state explosion problemthat often arises in composition of communicating systems.
Keywords
Arithmetic; Automatic logic units; Boolean functions; Data structures; Design methodology; Digital signal processing; Explosions; Formal verification; State-space methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1994. 31st Conference on
ISSN
0738-100X
Print_ISBN
0-89791-653-0
Type
conf
DOI
10.1109/DAC.1994.204176
Filename
1600449
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