Modeling of Intermediate Node States in Switch-Level Networks

An algorithm is presented for event-driven switch-level simulation of CMOS networks in which intermediate signal values are common. The proposed method is based on a local signal propagation scheme and an extended node model including both a logical low and a high contribution to the state of a node. The quantization effects of typical CMOS networks can thereby be modeled and, hence, the spread of undetermined logic values is in many cases prohibited.