Power Estimation in Digital CMOS VLSI Chips

Author

Tran, Duong ; Kim, Kyung Ki ; Kim, Yong-Bin

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA

Volume

1

fYear

2005

fDate

16-19 May 2005

Firstpage

317

Lastpage

321

Abstract

A method for estimating power consumption of digital CMOS VLSI chips is developed. The method estimates the total power consumption of a chip by analyzing separately for different parts of the chip, which are logic circuit, on chip memory, interconnection, clock distribution, and off chip driving. This method makes it possible to estimate the power consumption of a digital CMOS VLSI chip based on gate count, memory size, and logic circuit. An estimation tool, which is implemented in C language, is created and used to estimate the gate count from Verilog register transfer level (RTL) descriptions

Keywords

CMOS digital integrated circuits; VLSI; circuit analysis computing; low-power electronics; Verilog register transfer level; clock distribution; digital CMOS VLSI chips; gate count; logic circuit; off chip driving; on chip memory; power estimation; CMOS digital integrated circuits; CMOS logic circuits; CMOS memory circuits; Clocks; Energy consumption; Hardware design languages; Integrated circuit interconnections; LAN interconnection; Logic circuits; Very large scale integration; I/O; Verilog; clock distribution; inter-connection; logic circuit; on chip memory; power estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 2005. IMTC 2005. Proceedings of the IEEE

Conference_Location

Ottawa, Ont.

Print_ISBN

0-7803-8879-8

Type

conf

DOI

10.1109/IMTC.2005.1604125

Filename

1604125