DocumentCode :
452910
Title :
Circuit Testing Using Self-Nonself Discrimination
Author :
Souza, C.P. ; Freire, R.C.S. ; Assis, F.M.
Author_Institution :
Dept. of Electr. Eng., Fed. Univ. of Campina Grande
Volume :
2
fYear :
2005
fDate :
16-19 May 2005
Firstpage :
1186
Lastpage :
1189
Abstract :
Built-in self-test (BIST) techniques are rapidly becoming an industry-wide standard test technique in the design of testing support hardware for VLSI circuits. In the BIST setup both test pattern generation and output response analysis are performed on-chip hardware. In this manuscript a BIST scheme based on immune system is presented. The main conceptual ingredient utilized in order to build the proposed scheme is the application of the negative-selection mechanism of the immune system, which is able to discriminate between the self (body´s own cell) and any foreign cell (non-self). Experimental results concerning fault detection in some ISCAS85 benchmarks circuits are presented
Keywords :
VLSI; automatic test pattern generation; built-in self test; integrated circuit testing; BIST; VLSI circuits; built-in self-test; circuit testing; output response analysis; self-nonself discrimination; test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Hardware; Immune system; Pattern analysis; Performance analysis; Performance evaluation; Test pattern generators; Very large scale integration; Artificial Immune System; Built-in Self-Test; Circuit Testing; Self-Nonself Discrimination;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Instrumentation and Measurement Technology Conference, 2005. IMTC 2005. Proceedings of the IEEE
Conference_Location :
Ottawa, Ont.
Print_ISBN :
0-7803-8879-8
Type :
conf
DOI :
10.1109/IMTC.2005.1604333
Filename :
1604333
Link To Document :
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