A rigorous study of package and PCB effects on W-CDMA RFICs

Author

Han, F.Y. ; Wu, J.M. ; Horng, T.S. ; Tu, C.C.

Author_Institution

Dept. of Electr. Eng., National Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

2

fYear

2005

fDate

4-7 Dec. 2005

Abstract

This paper presents a practical evaluation method for package and PCB effects on RFICs in W-CDMA applications. The package and PCB interconnects are characterized rigorously by establishing their equivalent parasitic circuits with the help of the 3-D EM-simulation tool. For demonstration, two 1.9 GHz RFICs were fabricated by a GaAs HBT foundry process, and then housed in the leadless wirebond packages, and finally surface-mounted onto PCBs for testing. With the established equivalent parasite circuits, the package and PCB effects can be included in the RFIC simulation in the design stage. The simulated results agree quite well with the final measured results.

Keywords

III-V semiconductors; UHF integrated circuits; code division multiple access; equivalent circuits; gallium arsenide; heterojunction bipolar transistors; integrated circuit interconnections; integrated circuit packaging; lead bonding; printed circuit manufacture; surface mount technology; 1.9 GHz; 3D EM simulation; GaAs; GaAs HBT foundry process; PCB effects; PCB interconnects; RFIC; W-CDMA; equivalent parasitic circuits; interconnect effects; leadless wirebond packages; package effects; Bonding; Circuit simulation; Foundries; Gallium arsenide; Heterojunction bipolar transistors; Integrated circuit interconnections; Integrated circuit modeling; Multiaccess communication; Packaging; Radiofrequency integrated circuits; Interconnect effects; RFICs; package effects;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings

Print_ISBN

0-7803-9433-X

Type

conf

DOI

10.1109/APMC.2005.1606520

Filename

1606520