DocumentCode
453273
Title
FPGA implementation of downlink DBF calibration
Author
Wang, Zhen ; Jin, Rong ; Geng, Junping ; Fan, Y. ; Lian, Chun-Wei ; Chen, Jiann-Jong ; Yang, Guo-Min ; Wu, Qingyao
Author_Institution
Dept. of Electronic Engineering, Shanghai Jiao Tong University Shanghai 200030, China
Volume
3
fYear
2005
fDate
4-7 Dec. 2005
Abstract
The calibration system is very important in solving the amplitude and phase imbalance of the digital beam forming (DBF) antennas. In this paper, a hardware calibration system based on field programmable gate array (FPGA) is designed. The calibration algorithm adopted in this design is based on the parallel orthogonal codes. To improve the calibration speed, parallel design methods are used. The simulation result shows that this system can satisfy the request of the real time calibration of the downlink digital beam forming.
Keywords
Antenna arrays; Calibration; Downlink; Field programmable gate arrays; Logic gates; Calibration; DBF; FPGA; Parallel orthogonal codes; VHDL;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings
Conference_Location
Suzhou
Print_ISBN
0-7803-9433-X
Type
conf
DOI
10.1109/APMC.2005.1606686
Filename
1606686
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