Parallel processing of Powell´s optimization algorithm and its application to design of multi-way power dividers

In the case of optimizing the circuit configurations such as multi-way power dividers, the planar circuit approach is useful because of its merit of short calculation time. However, as the number of design variable increases, the CPU time required in the optimization becomes large. This paper describes a parallel computing technique of Powell´s optimization algorithm using a PC-cluster, and applies to an integration design of microstrip multi-way power dividers. As a result, it is shown that the parallel processing technique can speed up the circuit optimization with facility.