The design of integrated monolithic transformer for power IC

Author

Norhuzaimin, J. ; Chew, S.P. ; Kharuddin, A.H.

Author_Institution

Dept. of Electron., Malaysia Sarawak Univ.

fYear

2005

fDate

20-21 Dec. 2005

Abstract

This paper presents an intelligent technique of obtaining higher output power via low power supply by using on-chip transformer. Two separate 1:1 stacked and interleaved transformers have been fabricated with 0.25 mum VLSI technology. These on-chip transformers are designed and simulated using Virtuoso Layout Editor in CADENCE design software. Physical parameters of the transformers such as winding scheme, metal width and coupling coefficient have been proposed in this paper. An on-printed board stacked transformer with 15 times scaled-up, which using PROTEL software with experimental results are also presented and analyzed

Keywords

VLSI; integrated circuit design; power integrated circuits; transformers; 0.25 mum; VLSI technology; coupling coefficient; integrated monolithic transformer; on-chip transformer; on-printed board stacked transformer; power IC; Coupling circuits; Inductance; Inductors; Large scale integration; Parasitic capacitance; Power generation; Power integrated circuits; Power supplies; Radiofrequency integrated circuits; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Electromagnetics, 2005. APACE 2005. Asia-Pacific Conference on

Conference_Location

Johor

Print_ISBN

0-7803-9431-3

Type

conf

DOI

10.1109/APACE.2005.1607826

Filename

1607826