Improvement of differential planar spiral inductors on a 0.35μm BiCMOS process

An improved structure for integrated inductors which reduces effectively eddy currents induced into the lossy silicon substrate is introduced. The structure is based on a highly resistive area preventing currents in the substrate. Natural resources of an integrated circuit like pn-junctions are used to produce these areas. Estimation and optimization of the ideal distance between structure elements and reducing the inductor area are done. The effect is increased by connecting an external voltage supply to the structure. Measurement results show an increased quality factor of up to 20 which is an improvement of about 80%. A four layer thick metal 0.35μm BiCMOS process is used to reduce conductor resistance.