Low loss multi-wafer vertical interconnects for three dimensional integrated circuits

Author

Lahiji, Rosa R. ; Herrick, Katherine J. ; Mohammadi, Saeed ; Katehi, Linda P B

Author_Institution

Dept. of ECE, Purdue Univ., West Lafayette, IN, USA

Volume

1

fYear

2005

fDate

4-6 Oct. 2005

Abstract

A low loss multi-wafer vertical interconnect appropriate for a microstrip-based circuit architecture is proposed. This transition has been designed, fabricated and measured on 100 μm thick GaAs substrates. The measurements demonstrate insertion loss of better than 0.2dB and reflection of better than 13.6dB up to 20GHz. Using such a high performance transition allows for a more power efficient interconnect, while it enables denser packaging by stacking the substrates on top of each other, as today´s technologies demand.

Keywords

III-V semiconductors; gallium arsenide; integrated circuit interconnections; integrated circuit packaging; microstrip lines; 0.2 dB; 100 micron; 3D integrated circuits; insertion loss; integrated circuit packaging; microstrip line; microstrip-based circuit architecture; multiwafer vertical interconnects; Gallium arsenide; Insertion loss; Integrated circuit interconnections; Integrated circuit measurements; Loss measurement; Microstrip; Packaging; Reflection; Stacking; Thickness measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2005 European

Print_ISBN

2-9600551-2-8

Type

conf

DOI

10.1109/EUMC.2005.1608822

Filename

1608822