Parasitic extraction tool verification using an automatically generated set of ring oscillators

This paper describes a novel parasitic extraction methodology verification procedure for functional circuits and systems using automatically generated test structures. Ring oscillators are generated, extracted and simulated in a fully automated fashion and the results are used for technology benchmarking. Layouts of different structures for silicon-based technologies are generated using Matlab codes with Perl scripts. These structures are extracted to verify the performance of standard parasitic extraction (PEX) tools, comparing with an EM solver as a "gold standard". The ring oscillators are designed with a delay cell inserted between adjacent inverters cells so that the delay due to the parasitic structure dominates the delay due to active devices. To verify/standardize PEX tools, the delay cell topologies are varied considering possible parasitic effects in the available die area with defined process and layout parameters.