Power reduction in high-speed inter-chip data communications

Author

Kuroda, Tadahiro

Author_Institution

Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

1145

Lastpage

1149

Abstract

This paper describes power reduction techniques in high-speed inter-chip data communication with inductive coupled wireless interface for 3D-stacked SiP. NRZ signaling where signal is not transmitted when data holds reduces power dissipation in proportion to switching activity. A low-power single-end transmitter is presented for 55% transmitter´s power reduction. Depending on communication distance, transmit power is controlled for both power and crosstalk reduction. 195Gb/s, 1.2W high-speed and low-power interface with these techniques has been demonstrated in 0.25mum CMOS

Keywords

equivalent circuits; integrated circuit interconnections; low-power electronics; system-in-package; transmitters; 0.25 micron; 1.2 W; 195 Gbit/s; 3D stacked SiP; CMOS; NRZ signaling; crosstalk reduction; high-speed interface; inductive coupled wireless interface; inter-chip data communications; low-power interface; low-power single-end transmitter; power dissipation; power reduction; switching activity; CMOS technology; Coupling circuits; Crosstalk; Current density; Data communication; Equivalent circuits; Frequency; Inductors; Transmitters; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611234

Filename

1611234