Title :
Lithography-aware physical design
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX
Abstract :
Nanometer VLSI design is greatly challenged by the lithography limitations. Existing approaches in design for manufacturability (DFM) are mostly done post design, such as mask data preparation using various resolution enhancement techniques (RETs), rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper lithography metrics upstream to guide the proactive lithography aware physical design (LAPD). In this paper, we will discuss some key aspects of LAPD
Keywords :
VLSI; design for manufacture; integrated circuit design; nanolithography; design for manufacturability; lithography aware physical design; mask data preparation; nanometer VLSI design; resolution enhancement techniques; Bridges; Design for manufacture; Electronics industry; Interference; Lithography; Manufacturing; Routing; Semiconductor device manufacture; Timing; Very large scale integration;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611242
