DocumentCode :
453618
Title :
On-chip decoupling capacitor budgeting by sequence of linear programming
Author :
Qi, Zhenyu ; Hang Li ; Tan, Sheldon X.-D ; Cai, Yici ; Hong, Xianlong
Author_Institution :
Dept. of Electr. Eng., California Univ., Riverside, CA
Volume :
1
fYear :
2005
fDate :
24-0 Oct. 2005
Firstpage :
98
Lastpage :
101
Abstract :
Excessive power supply noise increases propagation delay of switching gates and reduces noise margin of the circuit. Adding on-chip decoupling capacitors (decaps) is an effective way to reduce voltage noise in a on-chip power delivery system. In this paper, we propose an efficient and novel algorithm to allocate decaps in an area efficient way. The new algorithm applies the sequence of linear programming based approach to searching the minimum decap area to reduce voltage drop below user specified threshold. We show existing sensitivity based decap allocation algorithms tend to over estimate the decap areas due to nonlinear sensitivity dependence on decap values. Experimental results show that the proposed algorithm uses significantly less decap area than the existing conjugate gradient based approach but with similar CPU runtimes
Keywords :
capacitors; circuit optimisation; linear programming; power supply circuits; conjugate gradient; decap allocation algorithms; excessive power supply noise; linear programming sequence; noise margin circuit reduction; nonlinear sensitivity dependence; on-chip decoupling capacitor budgeting; on-chip power delivery system; propagation delay; switching gates; Capacitors; Circuit noise; Linear programming; Noise reduction; Power supplies; Propagation delay; Runtime; Switching circuits; System-on-a-chip; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
Type :
conf
DOI :
10.1109/ICASIC.2005.1611252
Filename :
1611252
Link To Document :
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