Title :
A novel asynchronous multiple function multiply-accumulator
Author :
Gao, Jian ; Chen, Jie
Author_Institution :
IMECAS, Beijing, China
Abstract :
The paper describes a 16-bit high-speed and low-power multiply-accumulate unit (MAC) designed for DSP processor. The extreme power reduction derives from the asynchronous interlocked pipeline technique MAC adopts. And the speed is greatly increased by introducing the complemented partial product word correction (CP-PWC) algorithm and 3D reduction method (TDM) in the partial product generation and reduction. MAC shows low power dissipation and high speed and the DSP processor embedded with MAC has been implemented in 0.18 CMOS technology.
Keywords :
CMOS logic circuits; asynchronous circuits; digital signal processing chips; high-speed integrated circuits; low-power electronics; multiplying circuits; 16 bit; 3D reduction method; CMOS technology; DSP processor; asynchronous interlocked pipeline technique; complemented partial product word correction; multiply-accumulate unit; CMOS process; CMOS technology; Digital signal processing; Encoding; Pipelines; Power dissipation; Process design; Signal processing algorithms; Time division multiplexing; Very large scale integration;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611253
