DocumentCode
453620
Title
Design methodology of low power JPEG2000 codec exploiting dual voltage scaling
Author
Meng, Yicong ; Liu, Leibo ; Zhang, Li ; Wang, Zhihua
Author_Institution
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Volume
1
fYear
2005
fDate
24-27 Oct. 2005
Firstpage
227
Lastpage
231
Abstract
This paper proposed a novel dual voltage scaling layout architecture and a design methodology of low power JPEG2000 codec exploiting dual voltage scaling. Fabricated in SMIC 0.18μm 1P6M standard CMOS technology, this codec is capable of JPEG2000 compression/decompression with a 1280×1024 pixel (YUV422 full color) at 20 frames/s employing 100MHz operation frequency. And the power consumption is 465mW @ 1.8V and 100MH. Applied with dual voltage scaling technique, the power dissipation is reduced by 28.5%.
Keywords
CMOS digital integrated circuits; codecs; digital signal processing chips; image coding; integrated circuit layout; low-power electronics; 0.18 micron; 1.8 V; 100 MHz; 465 mW; CMOS technology; JPEG decompression; JPEG2000 compression; dual voltage scaling; low power JPEG2000 codec; CMOS technology; Circuits; Codecs; Delay; Design methodology; Dynamic voltage scaling; Image coding; Power dissipation; Transform coding; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611254
Filename
1611254
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