A low-swing differential interface circuit for high-speed on-chip asynchronous interconnection

Author

Yang, Huazhong ; Qiao, Fei ; Huang, Gang ; Wang, Hui

Author_Institution

Dept. of Electron. Eng., Tsinghua Univ., Beijing

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

1

Lastpage

5

Abstract

A novel low-swing interface circuit for asynchronous interconnection is proposed in this paper. It takes a level-triggered differential latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the method of driver-array (Fei Qiao et al., 2003) .The proposed circuit consumes less power than previously reported designs and can work up to 500 MHz, which is simulated and fabricated with SMIC 0.18-mum 1.8-V digital CMOS technology

Keywords

CMOS logic circuits; asynchronous circuits; driver circuits; flip-flops; high-speed integrated circuits; integrated circuit interconnections; low-power electronics; 0.18 micron; 1.8 V; 500 MHz; differential interface circuit; digital CMOS technology; digital signals; driver-array method; high-speed asynchronous interconnection; level-triggered differential latch; low-swing interface circuit; on-chip asynchronous interconnection; ultra low-swing voltage; CMOS technology; Circuit simulation; Driver circuits; Energy consumption; Frequency; Integrated circuit interconnections; Integrated circuit technology; Latches; Voltage; Wire; Driver-Array; low power; low-swing interface circuit;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611256

Filename

1611256