Floating-point unit processing denormalized numbers

Author

Zheng, Li ; Hu, He ; Yihe, Sun

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

6

Lastpage

9

Abstract

A hardware structure of floating-point unit (FPU) is presented. Four operations are supported, including: multiply-add-fused (MAF) operation A + (BtimesC), division, square-root operation, and conversion between fixed-point and floating-point numbers. The whole architecture is fully compliant with the IEEE 754 standard. In the MAF unit, the throughput is one operation per cycle, and the instructions are executed in three pipeline stages. Besides, rounding and denormalized inputs and outputs can be one-fly processed with little additional latency introduced. Radix-4 SRT iteration algorithms for both divides and square-root operations are used. A standard cell implementation for single precision calculation based on SMIC 0.18 mum CMOS technology has achieved

Keywords

CMOS digital integrated circuits; fixed point arithmetic; floating point arithmetic; iterative methods; pipeline processing; 0.18 micron; CMOS technology; FPU; IEEE 754 standard; MAF operation; denormalized numbers processing; fixed-point numbers; floating-point numbers; floating-point unit; multiply-add-fused operation; radix-4 SRT iteration algorithms; single precision calculation; square-root operation; CMOS technology; Delay; Frequency; Hardware; Helium; Logic; Microelectronics; Pipelines; Sun; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611257

Filename

1611257