Fast and efficiently binding of functional units for low power design

In this paper, we present a parallel optimizing algorithm for fast and efficiently binding the functional units in high-level synthesis, so as to minimize the power dissipations and run-times. It has been founded on the observation that different binding results will significantly affect the total number of switching activities (SW) of functional units, and further will affect the power dissipation. Also, the run-time for binding is considerable. Unlike many other previously proposed methods, our approach considers not only the minimizing of switching activities, but also the reducing of run-times for binding. Experimental results on benchmarks indicate that our designs are 11%-32% more power-efficient than the results produced by random binding. Furthermore, in terms of run-times as well as the switching activities, our approach makes an improvement on the circuit performance by 8.4% over the already existing power-optimized binding technique based on multistage graph methodology