Top-down implementation of pipelined AES cipher and its verification with FPGA-based simulation accelerator

This paper describes top-down implementation of Rijndael, a new advanced encryption standard (AES), cipher for both encryption and decryption. Pipelined architecture was used to maximize the performance. The design started in the untimed functional level description in C. It was refined to behavioral-level design and finally to RTL design with SystemC. To overcome simulation performance degradation with RTL description, we adopted FPGA-based simulation accelerator in the final stage. To reuse the original test vectors, we introduced proxy module for interconnecting simulation environment with acceleration environment. This hides the presence of simulation accelerator from simulator and makes it possible to reuse test vectors of RTL simulation when simulation accelerator is present