Bus buffer modeling and optimization for a microprocessor

Author

Wu, Xufan ; Yang, Jun ; Shi, Longxing

Author_Institution

Nat. ASIC Syst. Eng. Technol. Res. Center, Southeast Univ., Nanjing

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

137

Lastpage

141

Abstract

Inserting bus buffer is one significant method for solving the collisions in the microprocessor. And it is pivotal to determine the buffer size because of the performance and hardware resource constraints. This paper proposes a method for estimating the buffer size based on a prioritized M/G/1 queuing model and a high-level simulation model according to a RISC microprocessor. Both the results of queuing network model and the results of simulation model were found to be valuable. With the help of proposed simulation and estimating method, bus buffer size can be determined fast and accurately for the implementation

Keywords

buffer circuits; circuit optimisation; estimation theory; integrated circuit modelling; microprocessor chips; queueing theory; reduced instruction set computing; RISC microprocessor; bus buffer modeling; bus buffer optimization; hardware resource constraints; high-level simulation model; microprocessor collisions; prioritized M/G/1 queuing model; queuing network model; system-on-chip; Analytical models; Application specific integrated circuits; Decoding; Hardware; Liquid crystal displays; Microprocessors; Network servers; Optimization methods; Reduced instruction set computing; Wireless LAN; bus buffer; microprocessor; queuing model; simulation model; system-on-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611284

Filename

1611284