A design of 500MHz 10-read 6-write register file

Author

Qian, Yu ; Dong-hui, Wang ; Tie-jun, Zhang ; Chao-huan, Hou

Author_Institution

Inst. of Acoust., Chinese Acad. of Sci.

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

311

Lastpage

315

Abstract

Register file is needed to work in high speed for high performance superscalar processors to execute multiple parallel instructions. A 10-read 6-write write-through register file, customized in 1.8V 0.18mum CMOS technology, is introduced here, every port of which can be accessed individually. It comprises two arrays of modified 16-port memory cells, some low-power SCL decoders and a local clock generator, which is designed to enhance the range of working frequency. The results of the function verification and the performance analysis show that the register file can work in 500MHz with 46mW power consumption. The macro block´s area is 0.19mm. It can meet the requirements of both high performance processors and embedded ones

Keywords

CMOS digital integrated circuits; integrated circuit design; microprocessor chips; multiport networks; shift registers; 0.18 micron; 1.8 V; 46 mW; 500 MHz; CMOS technology; embedded processors; function verification; local clock generator; low power SCL decoders; memory cells; multiple parallel instructions; register file; superscalar processors; CMOS technology; Chaos; Circuits; Clocks; Decoding; Energy consumption; Frequency; Performance analysis; Random access memory; Registers; Customed; Register file; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611301

Filename

1611301