DocumentCode
453652
Title
Silent CMOS circuits aiming for system-on-chip
Author
Yuan, Jiren
Author_Institution
Competence Center for Circuit Design, Lund Univ., Sweden
Volume
1
fYear
2005
fDate
24-27 Oct. 2005
Firstpage
327
Lastpage
330
Abstract
A silent CMOS circuit architecture is proposed. Different silent CMOS gate solutions are presented and compared to the normal CMOS precharged gate in switching noise level. A silent 16-bit parallel carry-look-ahead adder is demonstrated. Simulation results on the circuits and the post layout of the adder are given, which shows a 10 times reduction in noise level is possible.
Keywords
CMOS digital integrated circuits; adders; carry logic; circuit noise; switching circuits; system-on-chip; 16 bit; noise level reduction; parallel carry look ahead adder; silent CMOS circuit architecture; switching noise; system-on-chip; Adders; CMOS logic circuits; Circuit noise; Circuit simulation; Clocks; Noise generators; Noise level; Protocols; Switching circuits; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611304
Filename
1611304
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