Area-efficient VLSI architecture of joint carrier recovery and blind equalization for QAM demodulator

In this paper, we propose an area-efficient architecture of joint carrier recovery and blind equalization, which is the kernel algorithm of QAM demodulation. The conventional architecture of joint carrier recovery and bind equalization occupies vast area in a QAM demodulator, so we optimize its architecture by means of MAC-sharing, interleaving, etc. Experimental results show that the proposed VLSI architecture reduces the circuit area evidently and improves the performance and stability.