Title :
A high-performance low-power 2D 8×8 IDCT processor with asynchronous pipeline
Author :
Ma, Xu ; Gao, Jian ; Chen, Jie
Author_Institution :
Inst. of Microelectron., Chinese Acad. of Sci., Beijing, China
Abstract :
This paper presents a high-performance low-power 2D IDCT processor for video applications. Based on multiply-accumulator architecture, the processor can meet the high-speed requirement of HDTV. To save power consumption, the processor employs asynchronous pipeline in which local clocks are enabled only when there is an operation to perform. Compared with conventional synchronous pipelined design, the proposed design exhibits an average power saving of 40%.
Keywords :
CMOS integrated circuits; asynchronous circuits; clocks; digital signal processing chips; discrete cosine transforms; high definition television; low-power electronics; pipeline processing; HDTV; asynchronous pipeline design; low power 2D IDCT processor; multiply-accumulator architecture; Bit rate; Capacitance; Clocks; Discrete cosine transforms; Energy consumption; HDTV; High performance computing; Matrix decomposition; Microelectronics; Pipelines;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611307
